At Eximius Design, our goal is to help you design your products efficiently

Our Engineering team has decades of experience developing products for a variety of product sectors, including consumer products, enterprise networking, microprocessors, cloud computing and data centers. We understand that each industry is different and has its own set of challenges and constraints. Whether it is power, performance or area, we can help you make the right tradeoffs and help design the right product.

Our engagement model is flexible. If you are a company without an ASIC team, we can develop an ASIC from nothing more than just a white-board discussion. If you are looking to diversify your portfolio, we can develop the ASIC for you. If you are looking to migrate an FPGA to an ASIC or to shrink process geometries, we can do it for you. If you just need help with one or more phases of an ASIC design such as verification or physical implementation, we can just as easily help you meet your goals efficiently.

  1. Product Definition
    • ASIC Feasibility studies (Area & Power estimation, Cost & Schedule estimation)
    • External IP selection & qualification
    • Microarchitecture & chip partitioning.
  2. Virtual Platform Development
  3. Functional (RTL) Design
  4. Block level & Full chip RTL verification
    • RTL design analysis, conformance checks against accepted coding standards and design rules.
    • Block level & full chip directed simulations
    • Block level & full chip constrained random simulations
  5. RTL Synthesis
  6. Design for Testability (DFT)
  7. Physical Implementation
  8. Package Design & Signal Integrity Analysis
  9. Debug Board Design
  10. Silicon Bring-up and Debug

Product Definition

If you just have a product idea in mind, we can help you develop a feasibility analysis. We can develop the ASIC microarchitecture, identify functionality that can be easily acquired externally, provide estimates for die-size, power, development cost and a schedule to built, debug & deliver a product that you can ship!

We have been building products for over 25years. In the last 10 years, we have built products at all process nodes from 130nm down to 28nm. For our own products, we have used a range of IP from all the leading IP vendors. They include

  • CPU cores for control & data plane processing.
  • High-speed serial interfaces such as USB, PCIe, Ethernet, SPI4.2
  • Mixed signal IPs such as ADC/DAC, PLLs, DDR PHYs

We have established excellent working relationship with these partners over this time frame.

Virtual Platform Development

Long before an ASIC is available, we can help you build simulation models that run several orders of magnitude faster than RTL simulations. These models can be used for architectural exploration, performance evaluation and to accelerate firmware development.

In the mobile application space, we have seen design cycles shrink from years to months. Now, more than ever, virtual platform development is necessary to guarantee first pass success and fast time to market.

Our engineering team has significant experience building models for the mobile application space. Contact us to learn more on how we can help speed up your time to market.

Functional (RTL) Design

Our team is exceptionally strong in the following areas.

  1. Designing Systems On a Chip (SOC) using single or multiple cores from ARM
  2. Designing high performance ASICs that require the right partitioning of functionality between fixed function units (“digital logic”) and data plane CPU cores.
  3. Integrating high speed serial interfaces (SERDES) on-chip.
  4. Integrating mixed signal IP such as Video DACs, ADC’s, and a variety of different sensors.
  5. Designing for low power using techniques such as Clock Gating, Power Islands or Power Gating.

Block level & Full chip RTL Verification

Over the last decade, newer languages such as SystemVerilog have allowed verification engineers to significantly improve their productivity in building and maintaining complex verification environments. The availability of a large body of pre-verified components provided by standardized methodologies such as eRM, VMM, OVM and UVM have also helped significantly.

Our team has experience building large maintainable verification environments in both SystemC & SystemVerilog. We can help preserve your investment in legacy simulation environments or help you build a new one from scratch.

Ineffective utilization of these newer verification techniques in some verification organizations has led to the following problems:

  • Increased use of license, compute and storage resources due to sub-optimal constraining of testbench stimulus.
  • Lack of predictability in verification schedules

Our verification team has been successful at avoiding these problems by not relying purely on a single verification methodology. Based on the complexity of the design-under-test (DUT), we engage one or more of the following methods.

  • Directed Test Cases
  • Constrained Random Verification using golden reference models
  • Assertion based verification
  • Formal verification to validate “ASIC-style” DUT against a golden reference model

We also use code & functional coverage metrics throughout our verification cycle to conserve simulation resources and assure predictability of schedule.


Our DFT team works very closely with the RTL design team in order to ensure proper compatibility with the design architecture. In addition, the DFT team works with the physical implementation team to ensure that during the implementation phase all clocking, timing, connectivity and congestion are accounted for. Overall this ensures a smooth and hassle free implementation while maintaining excellent test coverage.

Eximius Design offers a complete suite of DFT services including but not limited to the following:

  1. Scan Insertion
  2. Logic BIST
  3. Memory BIST
  4. Boundary Scan Insertion
  5. ATPG Compression
  6. Fault Simulation

Physical Implementation

Eximius Design provides a complete suite of physical implementation services focused on high-performance designs, low power designs and advanced processes. This includes synthesis, place and route, physical verification and final STA signoff. Based on our experience, commitment and motivation, our number one goal is to make sure our customer’s tapeout is a success.

Design Team and Experience

Eximius’s engineering teams have extensive experience in designing highly complex ASICs. Our tapeouts include network processors, graphic processors, low-power designs with design sizes ranging from 1 million gates to over 50 million gates across all major foundries.

Our design teams have deep knowledge in 28nm, 40nm, 65m, 90nm and 130nm technologies along with comprehensive experience in the selection, qualification and integration of third-party IP. Our technical staff has experience in all areas of physical implementation, including synthesis, floorplanning, placement, CTS, routing, STA, signoff, and physical verification just to name a few. With over numerous tapeouts, we know what must be done for a successful tapeout and product launch.


Our design methodology is build from a correct-by-construction concept ensuring quick turn around time and predictability. With a discipline and diligent approach to design, we are able to providing accurate timelines and schedules. Our highest priority is to provide first time silicon success. It’s absolutely critical that the physical implementation teams work with other teams such as, the system design team, package design teams, DFT teams to ensure a seamless process. Communication is the key to successful tapeout and eventual product launch and that is what Eximius provides. Eximius works with all industry standard tools, vendors and flows.

Design Process for RTL/Netlist to GDSII Handoff

With a defined 3-phase milestone approach with our customers, we’re able to identify issues, create solutions and provide feedback to customer teams during the entire physical implementation process and ensure an aggressive schedule to tapeout without sacrificing quality

Flexible Engagement Models

Eximius offers multiple engagement models for your physical implementation project Engagement Models

⇢ RTL/Netlist to GDSII
Eximius will take your design from RTL/Netlist to GDSII and perform all physical implementation activities in house to achieve a successful tapeout. This included synthesis, P&R, STA sign off and physical verification sign off

⇢ Project Management, Leadership and Staffing
Eximius can provide on-site staffing and consultant based off customer needs and timelines

⇢ Technical and Management Consulting
Eximius can provide technical consulting in times when design closure get tricky and expertise is needed in specific focused areas.

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